1. Technical Field
The present invention generally relates to microprocessors and in particular to speculative store buffers within microprocessors.
2. Description of the Related Art
A speculative store buffer is speculatively updated in response to speculative store memory operations buffered by a load/store unit in a microprocessor. Instead of performing dependency checking for load memory operations among the store memory operations buffered by the load/store unit, the load/store unit may perform a lookup in the speculative store buffer. The speculative store buffer holds values tentatively, allowing loads by the same hardware thread to read speculative values. Currently, the number of entries accepted into the speculative store buffers is limited. When the size limit of a speculative store buffer is attained, the speculative store buffer is no longer utilized, forcing the program utilizing the speculative store buffer to employ a different path of execution.
The size of buffers (such as reservation stations and the load/store buffer for storing memory operand requests or memory operations) may be increased to offset the delay in fetching memory operands. With increased buffer sizes, the capability of the microprocessor to detect parallelism in instruction code being executed is increased. Unfortunately, increased buffer size poses problems in program execution. Particularly, the load/store buffer performs dependency checking upon memory accesses to the data cache, to ensure that a prior store memory operation within the buffer is not bypassed by a subsequent load memory operation. As the number of buffer entries increases, the execution logic becomes more complex and requires increased evaluation time.